Many digital systems require high speed sampling of digital data signals. For example, in digital logic analyzers, digital phase locked loops (DPLL) and data and clock recovery circuits, there is a need to perform high speed sampling of digital data signals.
Sampling of digital signals is typically accomplished by applying the digital data signal to the input of a single latch which is clocked by a high speed clock. The output of the latch provides a sample of the value of the data signal each time a clock pulse is applied.
Unfortunately, there are limitations on the sampling rate or sampling frequency which is possible using a clocked latch. These limitations typically arise because of the inherent delay of the latch, including the latch set up time before the clock edge, the latch hold time after the clock edge, and the latch delay time in propagating a signal through the latch. Sampling rate may be increased by increasing the clock speed and/or minimizing the delays in the latch through use of higher speed technologies and circuit techniques. However, designs with higher speed clocks and higher speed technologies are generally more expensive.
Another technique for sampling of digital signals is described in a publication entitled A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-.mu.m CMOS by Kim et al., published in the IEEE Journal of Solid State Circuits, Vol. 25, No. 6, pages 1385-1393, December, 1990. A clock signal is propagated through a series of delay elements, and a tap after each delay element connects to the clock input of a corresponding latch. The data signal is connected to all the data inputs of the latches. The sampling rate is related to the delay between successive taps, which is typically determined by the delay of one or two inverters.